Abstract: We introduce here a novel layout-aware schematic-driven PIC design methodology: a circuit-level simulator supports the capability to specify directly physical locations and orientations of PDK building blocks (BBs) on the final layout (when required by DRC and packaging specifications or layout optimization) and to connect sub-circuits having fixed locations by smart elastic optical connectors. This allows combining graphical schematic capture and automated waveguide routing, which are currently considered separately representing a major problem for PIC designers. Key enabler for this functionality is the seamless integration of circuit and layout tools: a circuit simulator automatically and invisibly for users invokes a layout design tool to determine the actual physical lengths and shapes of all elastic connectors, constructs compact simulation models for them, and after that initiates the circuit simulations.

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